1. Field of the Invention
This invention relates to a static random access memory using static memory cells.
2. Description of the Related Art
In a static random access memory (SRAM), a plurality of static memory cells are connected in parallel between paired bit lines. These memory cells are selected responsive to the signals on word lines associated with the memory cells, respectively. In the SRAM, a minimum time required for reading out data from these memory cells varies depending on the potential on the bit lines immediately before the data is read out. In a practical use of the memory, there is a situation that data is written into a memory cell, and another data that is the inverted data previously written is read out from another memory cell connecting to the same bit line pair as that coupled with the data written memory cell. There is another situation that a data read mode has continued, and data is read out from a memory cell, and another data that is the inverted data previously read out, is read out from another memory cell. The read time in the former situation must be longer than that in the latter situation.
FIG. 1 shows a circuit diagram showing an arrangement around the memory cells in a conventional SRAM. A plurality memory cells MCn (n=any of positive integers except 0) are connected in parallel between paired bit lines BL and BL. These memory cells may be E/R type static memory cells. This type of memory cell, for example, MC1, is made up of a flip-flop 15 for data storage, and a couple of MOS transistors 16 and 17 as transfer gates. The flip-flop 15 consists of two MOS transistors 11 and 12 cross connected at the gates and the drains as shown, and two load resistors 13 and 14. The transfer gate transistors 16 and 17 are turned on and off in response to the signal on word line WL1.
As shown, two MOS transistors 21 and 22 as loads are respectively connected between the bit lines BL and BL and the power source voltage Vcc. The bit lines BL and BL are respectively connected to data lines DL and DL, through MOS transistors 23 and 24 for column decoding. The gates of these column decoding transistors 23 and 24 are applied with a decode signal CD from a column decoder (not shown). These transistors are turned on and off under control of the decode signal CD. Two load MOS transistors 25 and 26 are respectively connected between the data lines DL and DL, and the power source voltage Vcc.
The data lines DL and DL are coupled with write circuit 31 and read circuit 32. The write circuit 31 responds to complementary input data DIN and DIN, and outputs complementary write data for transfer to data lines DL and DL. When data is read out of the memory cells, the read circuit 32 amplifiers a potential difference between paired data lines DL and DL, and senses and outputs complementary data SO and SO.
In one memory cell MC1, for example, a storage state of data "1" places the cell circuit in such a state that transistor 11 is off, transistor 12 is on, node N1 connecting to resistor 13 is "1", and node N2 connecting to resistor 14 is "0". A data "0" storage state places the cell circuit in the reversed state.
To write data "0" to the memory cell MC1 in the SRAM, the input data DIN to write circuit 31 is set at "0", and data DIN is at "1". The result is that the write data of "0" is applied from write circuit 31 to data line DL, and write data of "1" to data line DL. Both the write data are transferred to paired bit lines BL and BL, through column decoding transistors 23 and 24. As a result, the node N1 in memory cell MC1 is forcibly pulled to "0" level. In turn, the transistor 12 cannot maintain its on state, and the potential at node N2 rises, and transistor 11 is turned on, and node N1 is set at "0". In this way, data "0" is written into memory cell MC1. Let us consider now that word line WL2 is selected immediately after this data write operation, and data "1" is read out from memory cell MC2. To read out data "1" from memory cell MC2 immediately after data "0" is written into memory cell MC1, the potential on bit line BL must be pulsed from "0" to "1", and the potential on bit line BL must be pulsed from "1" to "0". To rise the bit line BL potential from "0" to "1", it is necessary to charge the bit line BL by power source Vcc through load transistors 21 and 25. However, there is a limit in increasing the size of each transistor 21 and 25, and a subsequent limit in the conductance of the transistor. That is, a "0" level potential on the bit line BL and data line DL is determined by the size of transistors 21 and 25 and if the size of these transistors is increased there occurs an increase in their "0" level potential. For the same reason as set forth above it is not possible either to increase the size of transistors 22 and 26. This fact indicates that the bit line BL charge is not quick. At the start of data reading operation in read circuit 32, bit line BL rises from "0" to "1", and the potential on bit line BL falls "1" to "0". Subsequently, the potentials on either bit line will be inverted. From this level inverted point on, actual data read operation is allowed. To rise the potential on the bit line BL, it must be charged by load transistors 21 and 25 for a given time period. For this reason, when immediately after data is written into a memory cell, the data that is the inverted data previously written is read out from another memory cell connecting between the same paired bit lines, the read time of that data is longer time than that of other data.